• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    A device for supplying an inductive load comprises a switching structure adapted to control a current in the load, and an anomaly detection means adapted to generate a detection information or a non-detection information of an anomaly of the load. type of a short circuit that may appear in the wiring to the load, in combination with validity information of the non-anomaly detection information. The non-anomaly detection information is delivered without setting the validity information if the current measured at the end of a suitable time window is less than a determined current value.
    公开号:FR3013919A1
    申请号:FR1361534
    申请日:2013-11-22
    公开日:2015-05-29
    发明作者:Angelo Pasqualetto
    申请人:Continental Automotive GmbH；Continental Automotive France SAS；
    IPC主号:
    专利说明:

    [0001] The present invention relates generally to the supply of inductive loads. It relates more particularly to the detection of anomalies, such as short-circuits, which can appear in a switching structure such as a bridge of 5 transistors, for example, which is adapted to drive a current of determined value in an inductive load. The invention finds applications, in particular, in the automotive field. It can be implemented, for example, in an electronic circuit incorporating a switching structure such as a bridge of H transistors. In the automobile, such integrated circuits are used to control the direction and / or the intensity of electric current in inductive loads such as electric motors. These motors can be used in electronic control systems of an actuator. This may be for example a throttle control device (or ETC device, set for "Electronic Throttle Control" in English), or the flue gas recirculation valve (or EGR device, set to "Exhaust Gas Recirculation", or any other valve used in engine control or other. More generally, it may be any other equipment powered by an electric motor, such as a window regulator, for example. The supply of such inductive loads generally uses a switching structure such as an H-switch bridge. An H-bridge comprises four power switches, namely two "high" switches on the positive supply side. for example, a battery producing a positive supply voltage, and two "down" switches on the side of a negative power supply or ground. Each switch generally comprises a MOS transistor ("Metal Oxide Semiconductor" in English) power. A sequence of analog control signals of the four transistors is generated from a setpoint control signal. The setpoint signal and the analog control signals are generally pulse width modulated signals, or PWM (Pulse Width Modulation) signals. Their duty cycle makes it possible to control the amount of current injected into the inductive load and therefore, on average, the intensity of the current in this load. An example of a functional decomposition of an electronic control system according to a layered architecture is illustrated in FIG. 2. A hierarchically highest layer 21 named "application" layer makes it possible to choose a parameterization (initialization). The setpoint signal is generated at a layer 22 called "pilot" layer of the system, coming above a layer 23 or "control" layer, itself above a layer 24 or layer "hardware" constituted by the electronic elements of the H-bridge. At the level of the hardware and / or software implementation, the "command" 23 and "hardware" layers 24 can be produced in the same integrated circuit. The "application" 21 and "pilot" layers 22 can be implemented in the microprocessor of a car computer. A certain strategy causes the control of the H-bridge in certain determined configurations at the frequency of the reference signal. Other configurations are conversely prohibited, such as a configuration where a high switch and a low switch would be closed together by creating a short circuit between the battery and ground. Short-circuits may occur in the wiring between the outputs of the H-bridge, or between each of the outputs and the ground, or between each of the outputs and the positive voltage of the battery. The H-bridge protects itself by disjunct in a case of short circuit, and thus avoids its own destruction. The existence of a possible short-circuit can be verified by a current measurement passing through the power transistors. This measurement must be carried out during a period of the control signals, within a time window entirely comprised in a fraction of said period of the control signals where these do not change their electrical state, which obviously depends of the cyclical report. If the current measured during this reference time window exceeds a determined threshold, called short circuit current, an anomaly is declared to the "control" layer 23 of the system. However, at the level of the "pilot" layer 22, the general strategy is to filter out rare occurrences of failures, which would not be confirmed anyway during a diagnosis in a repair shop. In order to overcome a too sensitive detection, a confirmation mechanism can be implemented on several successive verifications. This mechanism can be based on an anomaly counter respectively associated with each of the anomalies considered. This anomaly counter can, for example, be kept up to date at the "application" layer 21 of the system, as a function of information relating to the presence or absence of the anomaly which is raised from the " hardware "24, via the layers" pilot "22 and" command "23, with each of the checks carried out. Thus, the anomaly counter is incremented if a check gives a positive result as to the presence of an anomaly, and can be decremented in the opposite case.
    [0002] However, it may happen that checks do not allow the detection of an anomaly yet very present. Such situations include, for example, the following non-limiting cases: impossibility of detecting a short circuit in the configuration of the H-bridge at the time of the verification (for example if the short-circuit sought is in parallel with a switch which is in the closed state in said configuration); - insufficient time available for the verification, compared to the time required to observe the abnormal rise of the current in the load allowing the detection of the short-circuit (taking into account the frequency and the duty cycle of the reference signal, and / or possibly because of the inductance of the short circuit); - insufficient short-circuit current (taking into account the voltage of the battery, and / or possibly the resistance of the short circuit).
    [0003] For this reason, the confirmation mechanism can also generate validity information associated with the non-anomalous information, in order to discriminate a situation of real absence of anomaly, of a situation of non detection of the anomaly. However, the anomaly is unclear as to the existence or absence of this anomaly. Indeed, the fact that an anomaly could not be detected during a given verification does not necessarily mean the absence of said anomaly. Thus, when information relating to the absence of anomaly is returned to the "pilot" layer 22, the anomaly counter is decremented only if, in addition, a validity bit is set. If the validity bit is not set, the counter is left in the state (neither incremented nor decremented).
    [0004] Anomaly detection devices that operate according to the above principle are relatively slow as to the validity bit. Indeed, current anomaly detection devices perform current measurement within a time window of fixed duration. In the absence of a short circuit, this duration can be between 30 and 55 ps. If a short circuit is detected, the validity bit is set upon detection, which is most likely done in a time well below 30 ps. Knowing that the duration during which the H-bridge remains in a given configuration depends on the duty cycle, and taking into account the range of duty cycle to be covered (ideally from 10% to 90% of the period of the reference signal, and in general at least 20% to 80% of this range), it turns out that the use of an anomaly bit in known devices is not satisfactory, in this example, for frequencies above 3.6 kHz. Beyond such a frequency, the detection of anomalies is not optimal, because the system is frequently in one of the cases mentioned above, so that many consecutive verifications give rise to a situation of uncertainty. resulting in the impossibility of taking into account the validity bit. Under these conditions, the use of the validity bit for the management of the anomaly counter as explained above, degrades the performance of the anomaly detection. For this reason, systems currently operating at frequencies greater than approximately 3.6 kHz do not use the validity bit. As a result, all situations of uncertainty regarding the existence or the absence of an anomaly are treated by the feedback of information relating to the non-detection of anomalies, without any other possible discrimination. This type of detection is likely to cause delays in the response to the "application" level 21 in the event of the presence of a real anomaly. In some cases, the known devices do not allow the detection of the presence of an anomaly. The invention proposes a management of the validity information, for example in the form of a validity bit as explained in the introduction above, which ensures a more efficient detection of anomalies. The proposed solution maintains the same level of reliability in anomaly detection even when the H-bridge is controlled at frequencies higher than 3.6 kHz due, among other reasons, to a higher accuracy of the circuit clock. integrated, an anticipation of the short circuit detection decision and the possibility of adjusting the duration of the reference time window at the application level. For this purpose, a first aspect of the invention proposes a device for supplying an inductive load comprising: a switching structure comprising at least one power switch, and adapted to drive a current in the load; abnormality detecting means adapted to generate detection information or non-detection information of a short-circuit-type anomaly, in combination with validity information of the non-detecting abnormality information which is not positioned by default, device in which the means for detecting anomalies comprise: current measuring means adapted to measure the current in the power switch in a detection time window during which the switching structure is maintained in a given configuration; - comparison means adapted to compare the measured current with a short-circuit current threshold and a intermediate current threshold below the short-circuit current threshold, and wherein the detection time window is constituted by a reference time window following the activation of the power switch and, if appropriate, by an auxiliary time window following an instant of exceeding the intermediate current threshold by the measured current, the comparison means are adapted to furthermore: - deliver the anomaly detection information and position the validity information if the measured current reaches the short-circuit current threshold before the end of the reference time window, - output the non-anomaly detection information and set the validity information, if the measured current remains below the current threshold intermediate until the expiration of the reference time window, - issue the non-anomaly detection information and set the information of validity if the measured current becomes greater than the intermediate current threshold before the end of the reference time window, but remains below the short-circuit current threshold until the end of the detection time window, - output the information detecting an abnormality and setting the validity information if the measured current becomes greater than the intermediate current threshold before the end of the reference time window, but becomes greater than the short-circuit current threshold before the end of the window temporal detection.
    [0005] The reduction of the time window necessary for generating the validity bit makes it possible to use such a validity bit even when the system is controlled at a frequency greater than 3.6 kHz. As a result, the accuracy of the anomaly detection mechanism is increased since only the effective detection of an absence of anomaly can lead to the decrementation of the anomaly counter.
    [0006] According to embodiments of the device, all or part of the following modalities can be provided: the device can furthermore comprise serial communication means adapted to allow the device to communicate with a control unit external to the device; can be adapted to transmit the anomaly information and the validity information to the "pilot" layer via the serial communication means, - the device can furthermore comprise first programmable memory means adapted to store modifiable values current thresholds, - the first programmable storage means can be programmable by the "pilot" layer via the serial communication means, - the device can further comprise second programmable storage means, adapted to store an editable value of the duration of the reference time window, and an editable value of the of the auxiliary time window, the second programmable memory means can be programmable by the "pilot" layer via the serial communication means, and the switching structure can comprise at least one power switch and be adapted to drive. the current in the load as a function of at least one control signal of the power switch, which is modulated in pulse width. In this case, the anomaly detection means can be adapted to operate by forcing the duty cycle to 100 `Vo. A second aspect of the invention relates to a method for supplying an inductive load using a device comprising: a switching structure comprising at least one power switch, and adapted to drive a current in a the load and, - abnormality detection means adapted to generate a detection information or a non-detection information of a fault of the type of a short circuit at the level of the wiring of the load, in combination with information validity of the non-anomaly detection information which is not positioned by default, the method comprising: - measuring the current in the power switch in a detection time window during which the switching structure is maintained in a determined configuration in which the power switch is closed and, - the comparison of the measured current with a short-circuit current threshold and an intermediate current threshold. ediaire less than the short-circuit current threshold, the detection time window consisting of a reference time window following the closing of the power switch and, if appropriate, an auxiliary time window following a time exceeding the intermediate current threshold by the measured current, the method further comprises, in addition: - the delivery of the anomaly detection information and the positioning of the validity information if the measured current reaches the threshold of short-circuit current before the end of the reference time window, - the delivery of the non-anomaly detection information and the positioning of the validity information, if the measured current remains below the intermediate current threshold until 'at the expiration of the reference time window, - the delivery of the non-detection of anomaly information and the positioning of the information of v ality if the measured current becomes greater than the intermediate current threshold before the end of the reference time window, but remains below the short-circuit current threshold until the end of the detection time window and, - the issuance of the anomaly detection information and the positioning of the validity information if the measured current becomes greater than the intermediate current threshold before the end of the reference time window, but becomes greater than the short-circuit current threshold before the end of the detection time window. Other features and advantages of the invention will become apparent on reading the description which follows. This is purely illustrative and should be read with reference to the accompanying drawings in which: - Figure 1 is a block diagram of an example of a switching structure comprising an H-bridge, - Figure 2, already described in the introduction, illustrative example of a functional decomposition of an inductive load supply system, according to a layered architecture, - Figures 3a, 3b, 3c are diagrams illustrating various control configurations of an inductive load by modulation of width of d Figure 4a and 4b are graphs showing a pulse width modulated periodic control command signal, and the corresponding evolution of the current in the inductive load. Fig. 5 is a block diagram of an exemplary control device according to embodiments, and, Figs. 6a, 6b, 6c, 6d, 6e, 6f show current graphs in a short circuit. -circuit l gèrement inductive function of time during a verification of the presence (or absence) of short-circuiting.
    [0007] Embodiments are described below in an exemplary application to an integrated circuit for controlling the direction and / or the intensity of the electric current in an inductive load such as an electric motor used in an automobile. As shown diagrammatically in FIG. 1, an H-bridge comprises four power switches, namely two "high" switches on the positive supply side, for example the battery of the vehicle producing a positive supply voltage Vbat, and two "low" switches on the side of a negative power supply or the vehicle ground Gnd. Such a switching structure comprises four switches, each having, for example, a power MOS transistor. A first transistor M1 is connected between a positive power supply terminal carried for example at the voltage of the battery Vbat, and a first node OUT1. A second transistor M2 is connected between said node OUT1 and a ground terminal Gnd. A third transistor M3 is connected between a second node OUT2 and the ground terminal Gnd. Finally, a fourth transistor M4 is connected between the positive power supply terminal Vbat and said second node OUT2. Transistors M1 and M4 are called high-side transistors and transistors M2 and M3 are called low-side transistors. The node OUT1 between the first high transistor M1 and the first low transistor M2 which are in series between Vbat and Gnd, corresponds to a first output of the bridge H. Similarly, the node OUT2 between a second high transistor M4 and a second transistor low M3 in series between Vbat and Gnd, corresponds to a second output of the bridge in H. The inductive load, for example an electric motor 1 in the example shown in Figure 1, is connected between the outputs OUT1 and OUT2 of the bridge in H.
    [0008] A sequence of analog signals S1 to S4 for controlling the four transistors M1 to M4, respectively, is generated from a setpoint control signal. The latter is generated at a "pilot" layer 22 of the system, coming above a "control" layer 23 in turn above a "material" layer 24 constituted by electronic elements of the H-bridge. properly so called.
    [0009] This sequence is produced according to a determined control strategy, depending on the application. Figure 2 shows the various layers decomposing the power system according to a given hierarchy, according to an exemplary embodiment. The elements and functionalities of the system are realized in hardware and / or software.
    [0010] The control strategy causes the control of the H-bridge in certain configurations. Other configurations are conversely prohibited, such as a configuration where the switches M1 and M2 would be closed together, in order to avoid connecting the battery 5 to ground Gnd. Typically, the H bridge can be controlled in three possible states or configurations, described below with reference to Figures 3a, 3b and 3c.
    [0011] In a first state, the pair formed of the high transistor M1 and the low transistor M3 makes it possible, when these transistors are on (closed switches), to circulate a current through the electric motor 1 in a first direction, from Vbat to Gnd, as indicated by an arrow in Figure 3a. Transistors M2 and M4 are then blocked (open switches).
    [0012] Conversely, in a second state, the pair formed of the low transistor M2 and the high transistor M4 makes it possible, when these transistors are on (closed switches), to circulate a current through the motor 1 in the other direction, still from Vbat. to Gnd, as indicated by the arrow in Figure 3b. Transistors M1 and M3 are then blocked (open switches).
    [0013] Finally, in a third state illustrated in FIG. 3c, the high transistors M1 and M4 are off (open switches) and the low transistors M2 and M3 are on (closed switches). This makes it possible to evacuate the energy accumulated in the inductive load, in the form of a current flowing towards ground Gnd through low transistors M2 and M3, as represented by the arrow in FIG. 3c. This state is called a freewheeling state. It can be controlled consecutively to an operation of the H-bridge in the first state or the aforesaid second state, after the opening of the high transistor M1 or the high transistor M4, respectively. It should be noted that the free wheel condition described above and shown in Figure 3c can also be achieved by other means. For example, when the high transistors M1 and M4 are on and the low transistors M2 and M3 are open. It is also possible to use structure diodes, allowing to have a single passing transistor, or even none. According to the strategy of controlling the H-bridge transistors, the decay of the current during freewheeling may differ. It will be appreciated that the invention is not limited by the type of switching structure. In particular, it also applies to a half-bridge switching structure, that is to say with two MOS transistors only power, or a switching structure with a single power switch only. Also, the embodiment of the power switch or switches shown in Figures 3a, 3b, 3c is only a non-limiting example. These switches may each comprise another type of field effect transistor (FET), a bipolar transistor (BJT, "Bipolar Junction transistor" in English), an IGBT transistor ("lnsulated Gate Bipolar Transistor"). In English), etc., instead of a MOS transistor, they may also include an assembly of such transistors, possibly with other components such as resistors, capacitors, etc. A so-called "application cabling" connecting the H-bridge to the load can be used thus allowing to control the latter.Physical anomalies can appear in the application wiring, in particular short-circuits at the outputs OUT1 and OUT2, in particular: - between the output OUT1 of the bridge in H and the mass Gnd, - between the output OUT1 of the H-bridge and the battery 5, - between the output OUT2 of the H-bridge and the ground Gnd, 10 - between the output OUT2 of the H-bridge and the battery 5, and in the OUT1 output and the OUT2 output of the H-bridge. They can be detected by measuring the current in the transistors, in the form of an abnormal rise in the current in certain configurations of the H-bridge. These short-circuits have some impedance (resistance and inductance). They are likely to affect the good functioning of the H bridge, and thus of the system comprising the controlled load. Detection of the short-circuit-type anomalies is implemented so that a suitable response can be provided, for example at the level of the "application" layer 21 of the system coming above the "pilot" layer 22. This response adapted can for example be part of the diagnostic features of the motor vehicle. So that the system is not subjected to too many false alarms by excessive sensitivity (for example on intermittent and rare short-circuits, or on an electromagnetic disturbance of the detection circuit), a feedback of information relating to a number of anomalies considered may use a confirmation mechanism on several consecutive verifications. This mechanism is based on an anomaly counter associated with each anomaly considered. An anomaly counter can be provided for each anomaly to be monitored. This anomaly counter can for example be kept up to date at the level of the "control" layer 23 of the system, as a function of information relating to the detection or non-detection of the anomaly that is raised from the " equipment "24 at each of the checks carried out. In embodiments, this mechanism implements a "validity bit", in order to discriminate a lack of duly verified anomaly of a situation of uncertainty as to the existence or not of an anomaly that may result from impossibility of verification, as in the cases stated in the introduction.
    [0014] With reference to the timing diagrams of FIGS. 4a and 4b, the current is controlled in the electric motor 1 by pulse width modulation of a periodic PWM reference signal. This signal has a given duty cycle, and is used to generate control signals for the transistors of the transistor bridge. The setpoint signal has a frequency that can reach 10 kHz, giving a period T of about 100 ps. As represented in FIG. 4a, such a PWM setpoint signal is, at each period T, in a first logical state determined among the logical high and low states during at least a first fraction of the period T, and in the other state during the remainder of the period T. In the example shown in FIG. 4a, the reference signal PWM is in the logic high state (active state) for a fraction of the period T having a duration tc, less than period T, called activation time. The dcom duty cycle dcom is given by: dcom = to / T (1) The dcom duty cycle dcom can vary between 0% and 100 `Vo. It is permissible for short-circuit detection to be fully operational only between 20% and 80%, but it is preferable for it to be between 10% and 90%. Figure 4b shows the evolution of the instantaneous value of the current 1M in the electric motor 1 obtained in response to the PWM reference command signal of Figure 4a. During the activation time of the PWM reference signal, that is to say, in the example, when this signal is in the high logic state, the current 1M in the electric motor 1 increases towards a nominal value determined . This nominal value corresponds to the ratio of the positive supply voltage divided by the value of a total resistance. The H-bridge is then controlled in the first or second state, illustrated in Figures 3a and 3b, respectively, depending on the direction of rotation of the electric motor 1 that is desired. During the period of deactivation of the PWM setpoint signal, i.e., in the example, when this signal is in the low logic state, the current lm decreases towards the null value. The H-bridge is then controlled in the third state, or freewheel state, illustrated in Figure 3c. Because of the inductive nature of the load constituted by the electric motor 1, the rise and fall of the current 1m are in a gentle slope, instead of following the shape of the square edges of the PWM reference signal. The average value <IM> of the current lm is given by: <lm> = dcbm × vbat x 1 / R (2) where R is essentially the value of the impedance of the electric motor 1. The other resistive elements are the values of the RDSON transition state resistors, and the resistance of wires, connections, and integrated circuit tracks.
    [0015] As discussed in the introduction, the anomaly checks are performed at the "control" layer 23 of the system, i.e., for example by measuring the actual current in the bridge power MOS transistors. H, in some configurations of it. When an anomaly is detected, the corresponding information is signaled to the "application" layer 21 of the system. When an information signaling an anomaly is returned to this layer, the anomaly counter maintained at this level is incremented. When, on the contrary, no anomaly is detected, the corresponding information is signaled to the microcontroller, and the validity bit then indicates whether the absence of detection of an anomaly corresponds to an actual absence of anomaly (to which case, for example, the validity bit is set, ie, is set to logical state 1) or only to the fact that an anomaly check could not be carried out or that the detection of a possible anomaly can not be guaranteed (in which case the validity bit is not set, ie is left in logical state 0 in the example, assuming that it was initialized to 0 on system route).
    [0016] When the anomaly counter exceeds a certain threshold, confirming on a succession of verifications the actual presence of the anomaly in the H-bridge, a corresponding information is produced at the level of the "application" layer 21. The sensitivity (c ') that is, the maximum allowable number) is set at this level. It will be appreciated that a plurality of anomaly counters may be maintained in parallel in the "application" layer 21, for example one for each type of anomaly and / or one for each anomaly that may be considered. An embodiment of a controller is shown schematically in Figure 5. Its operation will be explained below with reference to the graphs of Figures 6a, 6b, 6c, 6d and 6f. These graphs give the current measured in a transistor (M1, M2, M3 or M4) as a function of time, when the H-bridge is in a normal configuration, for example among those of FIGS. 3a and 3b, or in the configuration of FIG. 'A short-circuit. With reference to FIG. 5, the device 4 may be embodied as an integrated circuit, for example an ASIC ("Application Specific Integrated Circuit" in English), or the like. It can be coupled to a control unit 2, for example a microcontroller, a microprocessor, or the like, which is for example external to the device itself. However, in the vast majority of cases, the logic and control unit 2 is internal. It is for example carried out in the logic of the integrated circuit comprising MOS power transistors, which is in this case more commonly referred to as a "smart power" circuit which, in English, designates its intelligent power circuit function. The logic and control unit 2 may also be an independent integrated circuit. The MOS controlled power transistors then being so many separate components. The functionalities of the logic and control unit 2 correspond to a "control" layer 23 of the system, if one considers a layered model such as the one already referred to above, for the modeling of the system.
    [0017] The logic and control unit 2 receives as input control signals DIR and PWM. It outputs control signals S1, S2, S3 and S4 for the MOS transistors of the H-bridge feeding the electric motor 1, namely the transistors M1, M2, M3 and M4, respectively. On the input side of the logic and control unit 2, the signal DIR is, for example, a binary logic signal which controls the direction of rotation of the motor, that is to say the direction of flow of the current. across the H-bridge (see Figures 3a and 3b). The signal PWM is the reference command signal, with the duty cycle ratio of ,, which determines the amount of current supplying the load allowing for example to control the speed and / or the torque of the electric motor 1. The signals DIR and PWM come for example from the engine control computer, ie, the "application" layer 21 of the system, relayed by the "pilot" layer 22. The PWM signal has for example a frequency of about 10 kHz, which gives a period about 100 ps. The logic and control unit 2 further receives first signals Icc1, Icc2, Icc3, Icc4, on the one hand, and second signals int1, lint2, lint3, lint4 on the other hand. The first are representative of the detection or non-detection of a possible short circuit at the MOS transistors M1, M2, M3, M4 respectively. The second are representative of the exceeding of the intermediate current threshold by the measured current. Each of these first and second signals is for example a binary signal, ie, an information bit, which can take the logical value 1 or 0, to indicate the detection or the non-detection, respectively, of a short circuit or a a current exceeding the intermediate current threshold. These bits cause, under certain conditions which will be explained later, the counting / down counting of a contradiction counter managed in the logic and control unit 2. The value of this counter, named for example err count, allows to count the number of times that a short circuit is undetected at the end of the reference or detection time window, to then be detected outside these time windows.
    [0018] The means for comparing the currents flowing in the four power MOS transistors are represented by voltage comparators whose differential inputs are on either side of a low value resistor associated with each transistor. Such an arrangement would be able to achieve the desired function, and the current threshold would depend on the hysteresis value set at the voltage comparator. In an integrated circuit, it is preferred the use of current mirrors as well as current comparators to achieve the same functionality. But the representation would be a little more complex than what has been retained in FIG. 5. Whatever the technological realization, the first signals Icc1, Icc2, Icc3 and Icc4 are adapted to take logical values 0 or 1 according to the values current flowing through the MOS transistors. In one example, the signals Icc1, Icc2, Icc3 and Icc4 take the logic value 1 if the current flowing through the transistor concerned (respectively M1, M2, M3 or M4) is greater than a threshold I oc, that is to say a current corresponding to a short circuit.
    [0019] In addition, whatever the technological realization, the second signal signals lint1, lint2, lint3 and lint4 are adapted to take logical values 0 or 1 as a function of the values of the current flowing through the MOS transistors. For example, the signals lint1, lint2, lint3 and lint4 take the logic value 1 if the current flowing through the transistor concerned (respectively M1, M2, M3 or M4) is greater than a threshold I i, i.e. current high but substantially below a threshold I oc. It is of course possible to use inverse logic for the first signals and / or for the second signals (so that the logical value 0 would be the result of a current greater than the threshold). In another embodiment of the invention, the intermediate current threshold I int can be modified as well as the short-circuit current threshold I oc. The two thresholds I int and I oc are linked, it is preferable, to simplify the use of such a system that the selection of one (intermediate current threshold) causes the automatic selection of the other (current threshold short circuit). The choice of current thresholds is the "application" layer 21, and the information is relayed by the "pilot" layer 22 to the "control" layer 23, which configures the "hardware" layer 24, for example in a single phase. initializing. The communication means 3 which may comprise a serial bus, for example a SPI bus ("Serial Peripheral Interface" in English). Alternatively, it may be a type I2C serial interface, for example. If the current in a power MOS transistor does not reach the intermediate current threshold I int during the reference time window, the logic and control unit 2 sets a non-detection information with the validity bit. If in the continuation of the same measurement, the short-circuit current threshold I oc is exceeded in this transistor, the diagnosis is changed and the contrad count counter err count counts the event. It can be provided that, in all cases where the current in a transistor exceeds the threshold I oc, the logic and control unit 2 immediately stops the activation of the transistors, in order to avoid their destruction.
    [0020] The description of the control strategy and the response strategy implemented at the "application" layer 21 would be beyond the scope of the present description. The invention relates in fact to the management of the validity bit which is associated with the no-fault information at the level of the "hardware" layer 24. It aims at ensuring the generation of the validity bit in an optimized manner, so that this validity bit can be taken into account in the management of the value of the anomaly counter even when the control frequency of the H bridge is as high as 10 kHz, for example. The device also comprises a set of registers 4, which store a value T_diagl corresponding to the duration of a time window called reference time window, and the duration T_diag2 of an auxiliary time window, which will be discussed later. For example, these times can be expressed as a number of periods of the clock signal CLK. In one embodiment, the intermediate time window T_diagl is of modifiable duration, the corresponding register of the set of registers 4 being programmable for this purpose, for example under the control of the logic and control unit 2 via the bus 3. This makes it possible to adapt the operation of the device to the specific needs of the application. The duration T_diag2 can be fixed. In one embodiment, however, the duration T_diag2 is modifiable, as indicated above for the duration T_diagl. In embodiments, current comparators and registers 4 can be made on the same chip of semiconductor material as the H-bridge, for example in the ASIC. The operation of the device will now be detailed with reference in addition to Figures 6a, 6b, 6c, 6d, 6e and 6f. It is assumed that the H-bridge is controlled via the signals 51-54 in a configuration for measuring the current flowing in the transistors. For each transistor, the diagnosis management is illustrated in Figures 6a to 6f, depending on the various cases that may occur. In general, the variation of the current and more particularly the rise of the current takes place relatively slowly because it passes through an inductive load. The inductive load behaves, at the moment of the conduction of a transistor, as a current source, which absorbs its current either through the transistor in question, or through other paths (from the mass or the battery , through the structure diodes). Thus, when driving the electric motor 1, for a transistor participating in the current path, the current through this transistor very quickly reaches a value close to the current value corresponding to the end of the intermediate time window Tdiagl.
    [0021] This current value, during normal operation, is expected to be much lower than the intermediate value I int. On the other hand, in a case of permanent short-circuit, there is a sudden current rise on a much larger amplitude through a transistor concerned by the short-circuit. Unless a low battery voltage and a relatively highly resistive short-circuit, this current increases throughout the duration of activation of the transistor. If this time is long enough, for example 30 ps, the short-circuit threshold will be reached. As the detection of the short circuit therefore occurs in a shorter time, for example 15 ps, the comparison is made after this time, called Tdiagl, from the activation of the transistor concerned. It is therefore mainly to discriminate a case of current lower than I int after Tdiagl, other cases some of which are cases of short circuits. Some of the cases, where at the end of the duration Tdiagl the current is greater than I int, require additional time to recognize a short circuit, hence the use of another duration Tdiag2 which can extend Tdiagl. These cases are not frequent. They are, however, the subject of a description below, with reference to FIGS. 6c to 6f. In Figure 6a, two normal cases of non-short circuit are shown. For one of the cases, case A, the transistor does not participate in the freewheel, thus, when it is activated, the current in the inductive load remains practically constant while the switching of the current in the transistor is progressively a few microseconds, for example 3 microseconds. For the other case (case B shown in dashed lines), the transistor was activated during freewheeling and saw no sudden transient current through it. In both cases, at time t1, that is to say when the delay Tdiagl has elapsed, the current value reached 11 is less than the value I int. This makes it possible to record that there is no short circuit and to set the validity bit to 1. It is the logic and control unit 2 which draws up the diagnosis for each of the four transistors according to this principle. In Figure 6b, a short-circuit case is shown. The current increases rapidly and reaches the threshold I oc at time t2, before the expiration of the delay Tdiagl. At time t1, when the current reaches the threshold I int, the count of the duration Tdiag2 is started, but it is not useful in this case. The logic and control unit 2 records that there is a short circuit and sets the validity bit to 1 for the transistor concerned.
    [0022] In Figure 6c, a relatively resistive short-circuit case is shown. This short circuit would not be detected by a conventional circuit not using the invention. That is why the advance ruling should ideally be the same, that is, non-detection. The current increases rapidly to reach the threshold I int, at time t1, while the duration Tdiagl has not expired. It is not possible at this stage to predict that the threshold I oc will be crossed. From time t1, a complementary delay Tdiag2 is started and expires at a second time t2. At time t2, the current reaches the value 12 which is less than I oc. As a result, the logic and control unit 2 records that there is no short circuit and sets the validity bit to 1 for the relevant transistor.
    [0023] In Figure 6d, a relatively resistive short-circuit case is shown. The current reaches the short-circuit threshold in a relatively long time. During the duration Tdiagl, the current does not reach the threshold I oc but reaches the threshold 1_int at time t1. It is not possible to predict at time t1 whether the threshold I oc will be reached or not. The count of the complementary duration Tdiag2 is started at time t1. The current reaches the threshold I oc at time t3, before the duration Tdiag2 expires. At this time t3, the logic and control unit 2 records that a short circuit is detected and sets the validity bit to 1 for the transistor concerned. In Figure 6e, a case of relatively resistive short circuit is shown. This short circuit would not be detected by a conventional circuit not using the invention.
    [0024] This is why the advance ruling should ideally be the same, ie a non-detection decision. At time t1, the current reaches the threshold 1_int and, consequently, the counting of the complementary duration Tdiag2 is started. But this count is useless because it expires before the end of Tdiagl, which occurs at time t2. In the case shown, the current reaches the value 12, lower than the threshold I oc at time t2. The logic and control unit 2 records that there is no short circuit and sets the validity bit to 1 for the transistor concerned. In Figure 6f, a relatively resistive short-circuit case is shown. The current reaches the short-circuit threshold in a relatively long time. During the counting of the duration Tdiagl, the current reaches the threshold 1_int at time t1. It is not possible to predict at time t1 whether the threshold I oc will be reached or not before the end of the measurement. The count of the complementary duration Tdiag2 is started at time t1. This count is useless because its expiration arrives before the count of the duration Tdiagl. In the case shown, the current reaches the threshold I oc before the expiration of the duration Tdiagl. The logic and control unit 2 records that there is a short circuit and sets the validity bit to 1 for the transistor concerned. The operating principle of the method and the device for its implementation according to embodiments of the invention is illustrated in detail below.
    [0025] For each of the transistors, after a transition from the freewheel configuration to an activation configuration, or vice versa, the counting of the duration Tdiagl is started. If the current does not reach the threshold I int before the expiry of this count, then the validity bit is set to 1 and it is considered that there is no short circuit. The sequence can be abbreviated during operation when a new transition takes place. If the current reaches the threshold I int before the expiration of Tdiagl, then the counting of the delay time Tdiag2 is activated. If the current reaches the threshold I oc before the expiration of Tdiagl or Tdiag2, then the validity bit is set to 1 and the short circuit is taken into account. In the opposite case, when the threshold I oc is reached neither at the expiration of Tdiagl nor at the expiration of Tdiag2, then the validity bit is set to 1 and it is considered that there is no short circuit. Beyond the expiration of Tdiagl and Tdiag2, when no short circuit is detected, a new transition refers to the start of the process according to the invention.
    [0026] In embodiments, there is further provided a test for periodically verifying the consistency of the potential anomaly detection process. The test may consist of forcing the duty cycle of the PWM control signal to 100% and 0% for several periods of this signal during which an abnormality check is performed.
    [0027] This modification has the objective and the effect of testing the consistency of the results of the verifications of the presence of anomalies made previously. Indeed, by forcing the duty cycle to 100% and 0%, it is ensured that the maximum current possible is controlled in the transistors. Also, we have the maximum possible time (at the frequency of the PWM signal considered) to measure it. Thus, if a short circuit exists, it is more likely to be detected. In other words, the function of this debug test is to verify that the absence of short-circuit detection is valid, or if on the contrary a short-circuit can exist without having been detected. If the absence of detection of a short circuit is not confirmed by this test, ie, if a short circuit is detected during the test with d = 100% or 0% when it was not detected before, then a modification of the parameters of the checks can be carried out. For example, the duration of the intermediate time window Tdiagl can be modified. The above description has been given for illustrative purposes only, and is not limiting of the scope of the invention. Any technically feasible variant embodiment may be preferred to the embodiments described. For example, the err error counter can be realized using an external circuit or logic gates and an associated circuitry making it possible to perform the same function as that described in the invention. Likewise, the values of threshold currents and times of reference, auxiliary and detection time windows are given for illustrative purposes and are not limited to the examples given here and may be of any other value because of the embodiment system. . Finally, it is understood that the invention applies to the control of any inductive load, not only to that of an electric motor. It may be, for example, an electromagnetic actuator fixed coil and movable core (or vice versa).
    权利要求:
    Claims (10)
    [0001]
    REVENDICATIONS1. Device for supplying an inductive load (1) comprising: - a switching structure (M1 - M4) comprising at least one power switch, and adapted to drive a current in the load and - detection means for anomalies (5, 6) adapted to generate detection information or non-detection information of a fault of the type of a short circuit in the load wiring, in combination with information validity information non-detection of anomaly which is not positioned by default, wherein the means for detecting anomalies comprise: - current measuring means adapted to measure the current in the power switch in a detection time window (T diag) during which the switching structure is maintained in a predetermined configuration in which the power switch is closed and, - comparison means adapted to compare the measured current with u n short-circuit current threshold (I oc) and an intermediate current threshold (I int) lower than the short-circuit current threshold, and wherein, the detection time window (T diag) consisting of a reference time window (T diag1) following the closing of the power switch and, if necessary, an auxiliary time window (T diag2) according to a time (t1) of exceeding the intermediate current threshold (I Int) by the measured current, the comparison means are adapted to further: - deliver (Fig. 6b) the anomaly detection information and position the validity information if the measured current reaches the short-circuit current threshold (I oc) before the end of the reference time window (T diag1), - output (Fig. 6a) the non-anomaly detection information and position the validity information, if the measured current remains below the intermediate current threshold (I int) until the timeout of the reference time window ( T diag1), - output (Fig. 6c and 6e) the non-anomaly detection information and set the validity information if the measured current becomes greater than the intermediate current threshold (I int) before the end of the window reference time (T diag1), but remains below the short-circuit current threshold (I oc) until the end of the detection time window (T diag), and, - output (Fig. 6d and 6f) l anomaly detection information and position the validity information if the measured current becomes greater than the intermediate current threshold (I int) before the end of the reference time window (T diag1), but becomes greater than the short-circuit current threshold (I oc) before the end of the time window detection (T diag).
    [0002]
    2. Device according to claim 1, further comprising serial communication means (3), adapted to allow the device to communicate with a control unit external to the device.
    [0003]
    Device according to claim 2, adapted to transmit the anomaly detection information and the validity information to the external control unit via the serial communication means (3).
    [0004]
    4. Device according to any one of claims 1 to 3, further comprising first programmable storage means (4), adapted to store a modifiable value of the intermediate current threshold (I int), and a modifiable value of the threshold of short-circuit current (I oc). 20
    [0005]
    5. Device according to claim 4, wherein the first programmable storage means are programmable by the external control unit via the serial communication means (3).
    [0006]
    6. Device according to any one of claims 1 to 5, further comprising second programmable storage means (4), adapted to store an editable value of the duration of the reference time window (T diag1), and / or an editable value of the duration of the auxiliary time window (T diag2).
    [0007]
    7. Device according to claim 6, wherein the second programmable storage means are programmable by the external control unit via the serial communication means. 30
    [0008]
    8. Device according to any one of claims 1 to 7, wherein the switching structure is adapted to control the current in the load as a function of at least one control signal of the power switch which is modulated in width. pulse, and wherein the means for detecting anomalies are adapted to operate by forcing the duty cycle to 100 `Vo.
    [0009]
    9. Device according to claim 8, adapted to receive the control signal of the power switch from the external control unit.
    [0010]
    10. A method of supplying an inductive load (1) using a device comprising: - a switching structure (M1 - M4) comprising at least one power switch, and adapted to drive a current in the charging, - anomaly detection means (5, 6) adapted to generate a detection information or a non-detection information of a fault of the type of a short circuit at the load wiring, in combination with validity information of the non-anomaly detection information which is not positioned by default, the method comprising: - measuring the current in the power switch in a detection time window (T diag) during which the switching structure is maintained in a determined configuration in which the power switch is closed, - comparing the measured current with a short-circuit current threshold (I oc) and an intermediate current threshold (I int ) less than the short-circuit current threshold, the detection time window (T diag) being constituted by a reference time window (T diag1) following the closing of the power switch and, if appropriate, by an auxiliary time window (T diag2) following an instant (t1) of exceeding the intermediate current threshold (I Int) by the measured current, the method furthermore comprises, in addition: - delivery (FIG. 6b) of the anomaly detection information and the positioning of the validity information if the measured current reaches the short-circuit current threshold (I oc) before the end of the reference time window (T diag1) the delivery (Fig. 6a) of the non-anomaly detection information and the positioning of the validity information, if the measured current remains below the intermediate current threshold (I int) until expiry of the reference time window (T diag1), - the delivery (Fig. 6c and 6e) of the non-anomaly detection information and the positioning of the validity information if the current measured becomes greater than the intermediate current threshold (I int) before the end of the reference time window (T diag1), but remains below the short-circuit current threshold (I oc) until the end of the detection time window (T diag), - the delivery (Fig. 6d and 6f) of the anomali detection information e and the positioning of the validity information if the measured current becomes greater than the intermediate current threshold (I int) before the end of the reference time window (T diag1), but becomes greater than the short-circuit current threshold. circuit (I oc) before the end of the detection time window (T diag).
    类似技术:
    公开号 | 公开日 | 专利标题
    FR3013919A1|2015-05-29|SHORT-CIRCUIT DETECTION IN A SWITCHING STRUCTURE
    WO2015181112A1|2015-12-03|Field-effect transistor and associated fault detection device
    FR2723560A1|1996-02-16|POWER ASSISTED STEERING CONTROL DEVICE
    WO2020127672A1|2020-06-25|Device for automatic detection of coupling between electronic devices
    FR2924227A1|2009-05-29|METHOD FOR VERIFYING A MODULE OF DIGITAL OUTPUTS OF A PROGRAMMABLE AUTOMATE AND MODULE USING THE SAME
    WO2015124305A1|2015-08-27|Open-circuit detection in a switching structure
    FR2982998A1|2013-05-24|BATTERY OF ACCUMULATORS PROTECTED AGAINST SHORT CIRCUITS
    FR2893769A1|2007-05-25|CIRCUIT ARRANGEMENT WITH A SELF-DIAGNOSTIC SYSTEM FOR THE EXCITATION AND SUPERVISION OF A LOAD IN A BRIDGE CIRCUIT AND CORRESPONDING METHOD OF OPERATION.
    FR2907911A1|2008-05-02|Voltage controller for alternating current generator, has circuit detecting generator terminal voltage, where alarm signal is output when detected voltages of battery and terminal voltages are lower and higher than set value, respectively
    FR3006462A1|2014-12-05|METHOD AND DEVICE FOR READING THE STATE OF VARIABLES OF CONTACT OF A MOTOR VEHICLE
    FR2908939A1|2008-05-23|Main power bus voltage regulation assuring device for satellite, has control signal generating unit for generating control signal determining closing and opening of switch in specific cases
    FR3016442A1|2015-07-17|MEASUREMENT OF CONTACT RESISTANCE RESISTORS
    WO2018091830A1|2018-05-24|Device for protecting an electronic computer against a short circuit
    FR2923331B1|2019-06-21|ROTARY ELECTRICAL APPARATUS FOR AUTOMOBILE
    WO2016170262A1|2016-10-27|Voltage regulator of a motor vehicle alternator, regulator brush holder and corresponding alternators
    WO2018050991A1|2018-03-22|Method for supplying an inductive load
    EP2494564B1|2015-01-21|System for preventive diagnosis of contact impedance and overloads of a commutator
    EP3028356B1|2021-11-17|System for managing a supply voltage of an onboard electrical network of a motor vehicle
    WO2016097551A1|2016-06-23|Method and device for diagnosing an electric-energy management device
    FR3084468A1|2020-01-31|Method for diagnosing a switching means in a motor vehicle
    FR3087897A1|2020-05-01|METHOD FOR SUPPLYING AN INDUCTIVE LOAD
    EP1544050A1|2005-06-22|System for power supply of the functional elements of a vehicle electrical system
    FR3087898A1|2020-05-01|METHOD FOR SUPPLYING AN INDUCTIVE LOAD
    FR2920883A1|2009-03-13|METHOD FOR DETECTING A FAILURE ON A POWER SUPPLY SYSTEM OF AN ELECTRIC LOAD
    WO2019238666A1|2019-12-19|Method for detecting a malfunction of a voltage-limiting circuit and control system for implementing said malfunction-detecting method
    同族专利:
    公开号 | 公开日
    FR3013919B1|2016-01-08|
    US20150145553A1|2015-05-28|
    CN104656000A|2015-05-27|
    US9568560B2|2017-02-14|
    CN104656000B|2020-01-21|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    US7265535B2|2004-11-10|2007-09-04|Siemens Aktiengesellschaft|Circuit configuration for providing of a diagnostic signal for a power switching device|
    US20120249185A1|2011-03-31|2012-10-04|Analog Devices, Inc.|Protection circuit for driving capacitive loads|FR3037407A1|2015-06-15|2016-12-16|Continental Automotive France|DEVICE FOR DETECTING SHORT CIRCUITS OF H-BRIDGE|
    EP3299827A1|2016-09-23|2018-03-28|ALSTOM Transport Technologies|Method of detection of a short circuit in an electrical network comprising a transistor of igbt type and associated controlling device|JPH01321382A|1988-06-23|1989-12-27|Nec Ic Microcomput Syst Ltd|Test circuit for mos transistor|
    JPH0299455A|1988-10-06|1990-04-11|Omron Tateisi Electron Co|Motor drive device|
    US5457364A|1994-01-18|1995-10-10|Allegro Microsystems, Inc.|Bridge motor driver with short-circuit protection and motor-current limiting feature|
    CN1042582C|1994-05-18|1999-03-17|埃尔麦蒂克联合体|Optimal power supply for electric motor|
    CN1118934C|1997-11-22|2003-08-20|明和电子企业有限公司|Two-wire infrared inductive switch|
    US7339803B2|2004-04-09|2008-03-04|Eaton Corporation|Inverter bridge short-circuit protection scheme|
    DE102006030594B4|2006-07-03|2009-01-29|Continental Automotive Gmbh|Method and device for detecting a short circuit on a circuit arrangement|
    JP2009090749A|2007-10-05|2009-04-30|Nsk Ltd|Electric power steering device|
    JP5436230B2|2008-02-19|2014-03-05|株式会社島精機製作所|Inductive load drive circuit|
    US8629624B2|2010-08-18|2014-01-14|Lutron Electronics Co., Inc.|Method and apparatus for measuring operating characteristics in a load control device|
    JP5528998B2|2010-12-15|2014-06-25|株式会社アドバンテスト|Test equipment|
    US8816614B2|2011-09-29|2014-08-26|Infineon Technologies Ag|Diagnosis of over-current conditions in bipolar motor controllers|
    DE102011088912A1|2011-12-16|2013-06-20|Continental Automotive Gmbh|Circuit arrangement for detecting a short circuit in a circuit breaker assembly|
    JP2013225400A|2012-04-20|2013-10-31|Omron Corp|Abnormality detection device, program, and abnormality detection method|EP3428668A1|2014-06-30|2019-01-16|ELMOS Semiconductor AG|Method for obtaining an indication, in particular an initial indication of a possible faulty load condition of a polyphase electric motor|
    WO2017060031A1|2015-10-06|2017-04-13|Belimo Holding Ag|Actuator and method of operating the actuator|
    FR3042322B1|2015-10-07|2017-11-03|Continental Automotive France|METHOD FOR LIMITING CURRENT IN "H-BRIDGE" TYPE DEVICES|
    FR3047619B1|2016-02-08|2019-04-19|Continental Automotive France|DEVICE AND METHOD FOR CHARGE SYMMETRIC SWITCHING IN AN H-BRIDGE|
    US10746806B2|2016-03-22|2020-08-18|Infineon Technologies Ag|Transistor bridge failure test|
    DE102016220030A1|2016-10-14|2018-04-19|Robert Bosch Gmbh|Method for detecting a short circuit via a load|
    DE102017210870B3|2017-06-28|2018-10-04|Robert Bosch Gmbh|Device for measuring a thermal degradation of the cooling path power electronic components by means of luminescence|
    FR3075494B1|2017-12-19|2019-11-08|Continental Automotive France|METHOD FOR AT LEAST PARTIAL DELETION OF OSCILLATIONS ARISING AT THE END OF A CURRENT DISCHARGE FOR A H-BRIDGE|
    FR3080961A1|2018-12-19|2019-11-08|Continental Automotive France|Method for at least partial suppression of oscillations occurring at the end of a current discharge for an H-bridge|
    JP2021055286A|2019-09-27|2021-04-08|アイシン精機株式会社|Open-and-shut body driving system and its control method|
    法律状态:
    2015-11-19| PLFP| Fee payment|Year of fee payment: 3 |
    2016-11-18| PLFP| Fee payment|Year of fee payment: 4 |
    2017-11-21| PLFP| Fee payment|Year of fee payment: 5 |
    2019-11-20| PLFP| Fee payment|Year of fee payment: 7 |
    2020-11-20| PLFP| Fee payment|Year of fee payment: 8 |
    2021-04-16| TP| Transmission of property|Owner name: VITESCO TECHNOLOGIES, DE Effective date: 20210309 |
    2021-11-19| PLFP| Fee payment|Year of fee payment: 9 |
    2022-02-11| CA| Change of address|Effective date: 20220103 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1361534A|FR3013919B1|2013-11-22|2013-11-22|SHORT-CIRCUIT DETECTION IN A SWITCHING STRUCTURE|FR1361534A| FR3013919B1|2013-11-22|2013-11-22|SHORT-CIRCUIT DETECTION IN A SWITCHING STRUCTURE|
    US14/503,686| US9568560B2|2013-11-22|2014-10-01|Detection of a short-circuit in a switching structure|
    CN201410674096.XA| CN104656000B|2013-11-22|2014-11-21|Device and method for detecting short circuit in switch structure|
    [返回顶部]